A prior art clock system such as those used in digital cross-connect systems (DCS) is shown in FIG. 1 which illustrates clock circuits 120 and 121. One clock circuit is in an active mode whereas the other clock circuit is in a standby mode. Clock controllers 101 and 111 communicate via cable 110 and determine which clock circuit is active. If clock circuit 120 is active, then it drives clock buses 108 and 118 by the clock signals generated by phase locked loop 102. Clock controller 111 controls gates 115, 116, 117 so that the clock information on cable 109 is used to drive clock bus 118. Phase locked loop 112 utilizes the information received via cable 109 to align itself both in frequency and in phase with the output of phase locked loop 102.
In order to synchronize approximately the phases between clock buses 108 and 118, the output of phase locked loop 102 to bus 108 is delayed by delay line 104 to compensate for the nominal delay through gate 103, gate 117, and cable 109 to bus 118. When clock circuit 121 is active, similar functions are performed. However, there are problems with using a delay line to compensate for the delays through the semiconductor devices such as gates 103, 106, and 117. First, semiconductor devices have widely varying propagation delay times when the devices are not in the same physical package. Further, delay lines can not be temperature compensated for propagation delay shifts in the semiconductor devices, cables and within the delay line itself. Further, delay lines are notoriously unreliable devices.
The use of clock circuits such as clock circuits 120 and 121 has lead to severe limitations on duplicated digital switching systems. These limitations include having to place the clock circuits in very close proximity to each other and, in certain cases, within the same equipment shelf.
In addition, the use of such a clock system leads to the limitation on the architecture of the duplicated digital switching systems. This clock system normally allows error free switching between duplicated data signals only at relatively low speed interfaces which normally occur at the input and the output of the digital switching systems; but this clock system does not allow error free duplication switching in the high speed portions of the duplicated digital systems. This places a limitation on the switching architectures particularly in making digital switching systems more reliable. In addition, when the digital switching systems are switching high speed data at the inputs and the outputs, it is required to use high speed buffers at the input in order to compensate for the skew in clock signals from the duplicated clock circuits. The use of these high speed buffers at the inputs adds to the cost, power, and delay in such systems.
The problem is to provide duplicated clock signals matched in phase to within a few nanoseconds even when separated by hundreds of meters.